2. The width of this bus determines the maximum address that can be directly referenced:
Address
Data
Control
Interrupt

3. The width of this bus determines how many bits can be transferred simultaneously:
Address
Data
Control
Interrupt

4. Set of machine instructions that a processor recognises and can execute:
High level language
Low level language
Imperative language
Instruction set

5. Instruction which does not require an operand e.g. HALT:
Two address instruction
One address instruction
Zero address instruction
Shift instruction

6. Instruction for which two bytes are required for the operand, either because two operands are involved or because the operand is too large to fit into one byte e.g. MOV R1, R2:
Two address instruction
One address instruction
Zero address instruction
Shift instruction

7. Addressing mode where the operand is the address of a location which in turn holds the address of the data required:
Immediate (literal) addressing
Direct addressing
Indirect addressing
Relative addressing

8. Addressing mode where the operand is modified by adding the contents of the index register to give an address of the data:
Indirect addressing
Base register addressing
Relative addressing
Indexed (modified) addressing

9. Shift instruction where the MSB is discarded as all other bits move to the left:
Left logical
Left arithmetic
Right logical
Right arithmetic

10. Shift instruction which causes division by two and the sign bit is preserved:
Left arithmetic
Left logical
Right circular
Right arithmetic